1. Field of the Invention
The present invention relates to a device for jitter measurement and method thereof, and more particularly, to a device and a method that utilize the delay lines to implement the jitter measurement.
2. Description of Related Art
Jitter is a time shifting interval of a signal between a real transition location and an ideal transition location. As for a data transmission system, jitter would cause the incorrect operation of data transmission, and reduce the system reliability even cause error operation of the system. Jitter analysis has become more important in recent years due to high speed data calculation and signal transmission.
In traditional chip testing technology, the off-chip jitter measurement method utilizes an oscilloscope or a spectrum analyzer to measure the output signal of a chip for observing if the transition edges of the output signal fit in with expectation. However, the input and output (I/O) pads and bonding wirings often distort the output signal of the chip and reduce the accuracy of measuring results. The need of pin count often increases with the increase of transistor number in the chip. Nevertheless, the number of pins has not increased nearly as fast as the number of transistors due to mechanical limitation of the packaging technology. As a result, the pins that can be provided for testing are limited, and not all the signals-under-test (SUTs) can be accessed through independent pins. In digital signal processing, the pin count can be decreased by utilizing the serial transmission to transmit the signals-under-test. Nevertheless, the serial transmission can not be applied to the analog signal. The limit of pin counts and the unpredictable characteristic in transmitting the on-chip signal-under-test increase the testing difficulties of mix-signal chips. Therefore, a built-in self testing technology for jitter measurement is provided to overcome the above-mentioned problems.
The most important issue of the jitter measurement method by built-in self testing is to convert the continuous-time signal to a digital representation for the convenience of reading out and further processing. In the article with the title “A jitter characterization system using a component-invariant vernier delay line,” IEEE Trans. on Very Large Scale Integration System, pp. 79-95, 2004, a jitter measurement method utilizing component-invariant vernier delay line is provided. FIG. 1 is a circuit diagram of the conventional jitter measurement architecture according to the said article. Referring to FIG. 1, the jitter measurement device 100 includes the edge detectors 110 and 120, the ring oscillators 130 and 140, a phase detector 150 and a counter 160. The edge detectors 110 and 120 respectively convert a signal Data (referred as a signal-under-test) and a reference clock signal Clock to the step signals S1 and S2. The ring oscillators 130 and 140 respectively receive the step signals S1 and S2, and thereby generate the periodic pulse signals P1 and P2. The counter 160 records the oscillation times of the ring oscillators 130 and 140, and stops counting when the phase detector 150 detects the signal Data lagged the reference clock signal Clock.
The delay units 131 and 141 are respectively included in the ring oscillators 130 and 140, and designed to have different delay time τs and τf. It is supposed that the delay time τs is greater than the delay time τf by T1 seconds. The signal Data leads the reference clock signal Clock by T2 seconds, wherein T2>0, and the step signal S1 leads the step signal S2 by T2 seconds after edge detectors 110 and 120 are triggered. The delay time difference between the delay units 131 and 141 can be seen as a smallest resolution for measuring jitter. When the ring oscillators 130 and 140 accomplish one oscillation in the first time, a phase difference equaling (T2−T1) is existed between the pulse signals P1 and P2. To reason by analogy, when the ring oscillators 130 and 140 oscillate K times, the phase difference is (T2−K×T1). The counter 160 stops at the value K when the phase detector 150 detects the signal Data lagged the reference clock signal Clock, that is, (T2−K×T1)<0. Therefore, the edge detectors 110 and 120, the ring oscillators 130 and 140, the phase detector 150 and the counter 160 can be combined as a time-to-digital converter.
Although, the resolution which is less than the delay time of a logic gate for jitter measurement is achieved in the said article, the ring oscillators 130 and 140 may produce unwanted noises, and the delay time is not easy to control due to the affection of process variation and operation environment. Besides, an additional reference clock is necessary and more operation time is also necessary for obtaining enough sampling patterns in the said article. Those constraints should be taken into consideration to reduce the measuring difficulties.